Production Data
WM8580
DR4
DR3
S/PDIF TRANSMITTER
DATA SOURCE
S/PDIF received data
ADC digital output data
N/A
0
0
1
1
0
1
0
1
PAIF receiver data
Table 71 DR3 / DR4 Operation
The Secondary Audio Interface (SAIF) is not operational in Hardware Mode.
STATUS PINS
In Hardware control mode, SDO, SWMODE and MFP8/9/10 pins provide S/PDIF status flag
information.
FLAG
DESCRIPTION
PIN
SWMODE
UNLOCK
Indicates that the S/PDIF Clock Recovery circuit is unlocked
or that the input S/PDIF signal is not present.
0 = Locked to incoming S/PDIF stream.
1 = Not locked to the incoming S/PDIF stream, or incoming
stream not present.
SDO
NON_AUDIO
Logical OR of PCM_N and AUDIO_N:
PCM_N indicates that non-audio code (defined in IEC-61937)
has been detected. AUDIO_N is the recovered Channel
Status bit-1.
MFP8
MFP9
C
Recovered channel-bit for current sub-frame
SFRM_CLK
Indicates current sub-frame:
1 = Sub-frame A
0 = Sub-frame B
MFP10
192BLK
Indicates start of 192-frame block. High for duration of frame
0, low after frame 0.
Table 72 Hardware Mode Status Pins
DIGITAL AUDIO INTERFACE CONTROL
In Hardware Control Mode, CSB and SCLK become controls to configure the Primary Audio Interface
data format and word length. The configuration applies to both transmit and receive sides of the
interface. Table 73 below shows the options available.
CSB
SCLK
FORMAT & WORD LENGTH
24-bit right justified
20-bit right justified
24-bit left justified
24-bit I2S
0
0
1
1
0
1
0
1
Table 73 Audio Interface Hardware Mode Control
DAC MUTE CONTROL
In Hardware Control mode, the MUTE pin activates the softmute function on all the DACs. In
Software Control mode, MUTE activates softmute on the DAC selected by the DZFM register (when
the MPDENB bit is low). See section headed “MUTE MODES” for a detailed description of the
softmute function and the other methods of activating softmute.
When floating, the MUTE pin becomes an output for the ZFLAG flag.
PD Rev 4.3 August 2007
73
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
