Production Data
WM8580
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R50
PWRDN 1
32h
0
PWDN
0
Master powerdown (overrides all
powerdown registers)
0 = All digital circuits running,
outputs are active
1 = All digital circuits in power
down mode, outputs muted
1
ADCPD
1
ADC powerdown
0 = ADC enabled
1 = ADC disabled
DAC powerdowns
0 = DAC enabled
1 = DAC disabled
DACPD[0] = DAC1
DACPD[1] = DAC2
DACPD[2] = DAC3
Overrides DACPD[3:0]
4:2
DACPD[2:0]
111
6
0
ALLDACPD
OSCPD
1
0
0 = DACs under control of
DACPD[3:0]
1= All DACs are disabled.
OSC output powerdown
0 = OSC output enabled
1 = OSC output disabled
R51
PWRDN 2
33h
A CMOS input can be applied to
the OSC input when powered
down.
1
2
3
PLLAPD
PLLBPD
SPDIFPD
1
1
1
0 = PLLA enabled
1 = PLLA disabled
0 = PLLB enabled
1 = PLLB disabled
S/PDIF Clock Recovery
PowerDown
0 = S/PDIF enabled
1 = S/PDIF disabled
4
5
SPDIFTXD
SPDIFRXD
1
1
S/PDIF Transmitter powerdown
0 = S/PDIF Transmitter enabled
1 = S/PDIF Transmitter disabled
S/PDIF Receiver powerdown
0 = S/PDIF Receiver enabled
1 = S/PDIF Receiver disabled
Table 67 Powerdown Registers
PD Rev 4.3 August 2007
69
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
