WM8580
Production Data
REGISTER NAME
ADDRESS
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
R39
R40
R41
R42
R43
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
GPO2
GPO3
GPO4
GPO5
GPO4OP[3:0]
GPO6OP[3:0]
GPO8OP[3:0]
GPO10OP[3:0]
GPO30P[3:0]
GPO5OP[3:0]
GPO70P[3:0]
GPO9OP[3:0]
000110010
001010100
001110110
010011000
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
ALWAYSVALID
0
0
0
INTSTAT
SPDRXCHAN 1
SPDRXCHAN 2
SPDRXCHAN 3
SPDRXCHAN 4
SPDRXCHAN 5
SPDSTAT
Error Flag Interupt Status Register
Channel Status Register 1
Channel Status Register 2
Channel Status Register 3
Channel Status Register 4
Channel Status Register 5
S/PDIF Status Register
R44
R45
R46
R47
R48
R49
R50
R51
PWRDN 1
0
0
0
ALLDACPD
1
DACPD[2:0]
ADCPD
PWDN
001111110
000111110
PWRDN 2
0
0
0
0
SPDIFRXD
0
SPDIFPD PLLBPD PLLAPD OSCPD
SPDIFTXD
READEN
0
CONTREAD
READMUX[2:0]
R52
R53
34
35
READBACK
RESET
000000000
n/a
RESET
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Fractional (K) part of PLLA frequency ratio (R).
R0
PLLA 1/
DEVID1
00h
8:0
PLLA_K[8:0]
100100001
Value K is one 22-digit binary number spread over registers R0,
R1 and R2 as shown.
Reading from these registers will return the device ID.
R0 returns 10000000 = 80h
R1
8:0
PLLA_K[17:9]
101111110
PLLA 2/
DEVID2
01h
R1 returns 10000101 = 85h
Device ID readback is not possible in continuous readback mode
(CONTREAD=1).
R2
3:0
7:4
PLLA_K[21:18]
PLLA_N[3:0]
1101
0111
PLLA 3/
DEVREV
02h
Integer (N) part of PLLA frequency ratio (R).
Use values in the range 5 ≤ PLLA_N ≤ 13 as close as possible to
8.
Reading from this register will return the device revision number.
PLL Pre-scale Divider Select
R3
PLLA 4
03h
0
1
PRESCALE_A
0
0
0 = Divide by 1 (PLL input clock = oscillator clock)
1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2)
Note: PRESCALE_A must be set to the same value as
PRESCALE_B in PLL S/PDIF receiver mode.
POSTSCALE_A
PLL Post-scale Divider Select
PLL S/PDIF Receiver Mode
POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK,
POSTSCALE_B is not used. Refer to Table 45.
PLL User Mode
Used in conjunction with the FREQMODE_x bits. Refer to Table
44.
4:3
FREQMODE_A[
1:0]
10
PLL Output Divider Select
PLL S/PDIF Receiver Mode
FREQMODE_A is automatically controlled. FREQMODE_B is not
used.
PLL User Mode
Used in conjunction with the POSTSCALE_x bits. Refer to Table
44.
PD Rev 4.3 August 2007
76
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
