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WM8580_07_12 参数 Datasheet PDF下载

WM8580_07_12图片预览
型号: WM8580_07_12
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道编解码器S / PDIF收发器 [Multichannel CODEC with S/PDIF Transceiver]
分类和应用: 解码器编解码器光电二极管
文件页数/大小: 97 页 / 1142 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8580  
NON-AUDIO DETECTION  
The SPDIF payload can contain PCM data for audio or non-audio applications. In the case where the  
payload contains the 96 bit synchronization code defined in IEC61937 then this indicates that the  
payload contains data which is not suitable for direct playback through an audio codec.This 96 bit  
code is defined as 4*16bits of ‘0’+Pa (16bits)+Pb (16bits)..  
If the SPDIFRx interface decodes this sync code then it sets the PCM_N bit.  
When the PCM_N =1, then it indicates non-audio data. When the PCM_N =0, then it indicates that  
the SPDIF payload does not contain the synch code..  
Another status bit, AUDIO_N status is recovered from the Channel Status block.It is bit 1 of the  
channel status. When AUDIO_N =0, then it indicates that the SPDIF payload contains audio PCM  
encoded data. This is also referred to as linear PCM data.When the AUDIO_N= 1, then it indicates  
that the SPDIF payload does not contain audio PCM data.  
NON_AUDIO data is indicated by a logical OR of the AUDIO_N and PCM_N flags.  
If DAC1 is sourcing the S/PDIF Receiver and either the AUDIO_N or PCM_N flags are asserted,  
DAC1 is automatically muted using the soft mute feature. As described above, any change of  
AUDIO_N or PCM_N status will cause an INT_N interrupt (UPD_NON_AUDIO) to be generated. If  
the MASK register bit for AUDIO_N or PCM_N is set, then the associated signal will not generate an  
interrupt (UPD_NON_AUDIO) but the DAC will be muted.  
S/PDIF INPUT/ GPO PIN CONFIGURATION  
The WM8580 has ten pins which can be configured as GPOs using the registers shown in Table 66.  
The GPO pins can be used to output status data decoded by the S/PDIF receiver. These same pins  
may be used as S/PDIF inputs as described in Table 55.  
REGISTER  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
ADDRESS  
R38  
3:0  
7:4  
GPO1OP[3:0]  
GPO2OP[3:0]  
0000  
0001  
0000 = INT_N  
0001 = V  
GPO1  
26h  
0010 = U  
0011 = C  
R39  
3:0  
7:4  
GPO3OP[3:0]  
GPO4OP[3:0]  
0010  
0011  
0100 = P  
GPO2  
27h  
0101 = SFRM_CLK  
0110 = 192BLK  
0111 = UNLOCK  
1000 = CSUD  
1001 = Invalid  
1010 = ZFLAG  
1011 = NON_AUDIO  
1100 = CPY_N  
1101 = DEEMP  
R40  
3:0  
7:4  
GPO5OP[3:0]  
GPO6OP[3:0]  
0100  
0101  
GPO3  
28h  
R41  
3:0  
7:4  
3:0  
7:4  
GPO7OP[3:0]  
GPO8OP[3:0]  
GPO9OP[3:0]  
0110  
0111  
1000  
1001  
GPO4  
29h  
1110 = Set GPO as S/PDIF input (CMOS-compatible  
input). Only applicable for GPO3/4/5.  
R42  
GPO5  
2Ah  
1111 = Set GPO as S/PDIF input (‘comparator’ input for  
AC coupled consumer S/PDIF signals). Only applicable  
for GPO3/4/5  
GPO10OP  
[3:0]  
Table 66 GPO Control Registers  
PD Rev 4.3 August 2007  
67  
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