WM8580
Production Data
2. In 24 bit I2S mode, any data width of 24 bits or less is supported provided that LRCLK is high for
a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles. If exactly 32 bit
clocks occur in one full left/right clock period the interface will auto detect and configure a 16 bit
data word length.
DAC FEATURES
DAC INPUT CONTROL
The Primary Audio Interface Receiver has a separate input pin for each stereo DAC. Any input pin
can be routed to any DAC using the DACSEL register bits.
REGISTER ADDRESS
BIT
LABEL
DAC1SEL
[1:0]
DEFAULT
DESCRIPTION
R15
DAC Control 1
0Fh
1:0
00
DAC digital input select
00 = DAC takes data from DIN1
01 = DAC takes data from DIN2
10 = DAC takes data from DIN3
3:2
5:4
DAC2SEL
[1:0]
01
10
DAC3SEL
[1:0]
Table 17 DAC Input Select Register
DAC OVERSAMPLING CONTROL
For sampling clock ratios of 256fs to 1152fs the DACs should be programmed to operate at 128
times oversampling rate. For sampling clock ratios of 128fs and 192fs, the DACs must be
programmed to operate at 64 times oversampling rate. The DACOSR register bit selects between
128x and 64x oversampling.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC Oversampling Rate Control
0= 128x oversampling
R12
PAIF 3
0Ch
6
DACOSR
0
1= 64x oversampling
Table 18 DAC Oversampling Register
PD Rev 4.3 August 2007
30
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