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WM8580_07_12 参数 Datasheet PDF下载

WM8580_07_12图片预览
型号: WM8580_07_12
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道编解码器S / PDIF收发器 [Multichannel CODEC with S/PDIF Transceiver]
分类和应用: 解码器编解码器光电二极管
文件页数/大小: 97 页 / 1142 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8580  
DAC DIGITAL VOLUME CONTROL  
The DAC volume may also be adjusted in the digital domain using independent digital attenuation  
control registers  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R20  
7:0  
LDA1[7:0]  
11111111  
(0dB)  
Digital Attenuation control for DAC1 Left Channel (DACL1) in 0.5dB  
steps. See Table 23  
Digital  
Attenuation  
DACL 1  
8
UPDATE  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store LDA1 in intermediate latch (no change to output)  
1 = Apply LDA1 and update attenuation on all channels  
14h  
R21  
7:0  
8
RDA1[6:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC1 Right Channel (DACR1) in  
0.5dB steps. See Table 23  
Digital  
Attenuation  
DACR 1  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store RDA1 in intermediate latch (no change to output)  
1 = Apply RDA1 and update attenuation on all channels.  
15h  
R22  
7:0  
8
LDA2[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC2 Left Channel (DACL2) in 0.5dB  
steps. See Table 23  
Digital  
Attenuation  
DACL 2  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store LDA2 in intermediate latch (no change to output)  
1 = Apply LDA2 and update attenuation on all channels.  
16h  
R23  
7:0  
8
RDA2[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC2 Right Channel (DACR2) in  
0.5dB steps. See Table 23  
Digital  
Attenuation  
DACR 2  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store RDA2 in intermediate latch (no change to output)  
1 = Apply RDA2 and update attenuation on all channels.  
17h  
R24  
7:0  
8
LDA3[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC3 Left Channel (DACL3) in 0.5dB  
steps. See Table 23  
Digital  
Attenuation  
DACL3  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store LDA3 in intermediate latch (no change to output)  
1 = Apply LDA3 and update attenuation on all channels.  
18h  
R25  
7:0  
8
RDA3[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC3 Right Channel (DACR3) in  
0.5dB steps. See Table 23  
Digital  
Attenuation  
DACR3  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store RDA3 in intermediate latch (no change to output)  
1 = Apply RDA3 and update attenuation on all channels.  
19h  
R28  
7:0 MASTDA[7:0]  
11111111  
(0dB)  
Digital Attenuation control for all DAC channels in 0.5dB steps. See  
Table 23  
Master Digital  
Attenuation  
8
UPDATE  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store gain in intermediate latch (no change to output)  
1 = Apply gain and update attenuation on all channels.  
1Ch  
Table 22 Digital Attenuation Registers  
Note: The volume update circuit of the WM8580 has two sets of registers; LDAx and RDAx.  
These can be accessed individually, or simultaneously by writing to MASTDA - Master  
Digital Attenuation. Writing to MASTDA will overwrite the contents of LDAx and RDAx.  
PD Rev 4.3 August 2007  
33  
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