Production Data
WM8580
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The
WM8580 can be configured using the Control Interface. All unused bits should be set to ‘0’. Not all registers can be read. Only the
device ID (registers R0, R1 and R2) and the status registers can be read. These status registers are labelled as “read only”
REGISTER NAME
ADDRESS
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
R0
00
01
02
03
04
05
06
07
PLLA 1/DEVID1
PLLA_K[8:0]
PLLA_K[17:9]
100100001
101111110
001111101
000010100
100100001
101111110
001111101
110010100
R1
R2
R3
R4
R5
R6
R7
PLLA 2/DEVID2
PLLA 3/DEVREV
PLLA 4
0
0
PLLA_N[3:0]
0
PLLA_K[21:18]
1
FREQMODE_A[1:0]
0
0
POSTSCALE_A PRESCALE_A
PLLB 1
PLLB_K[8:0]
PLLB_K[17:9]
PLLB 2
PLLB 3
0
PLLB_N[3:0]
PLLB_K[21:18]
MCLKOUTSRC[1:0]
FREQMODE_B[1:0]
PLLB 4
CLKOUTSRC[1:0]
1
POSTSCALE_B PRESCALE_B
CLKSEL
_MAN
R8
08
0
0
0
TX_CLKSEL[1:0]
ADC_CLKSEL[1:0]
DAC_CLKSEL[1:0]
000010000
CLKSEL
R9
09
0A
0B
0C
0D
0E
0F
10
11
12
13
PAIFRXMS_CLKSEL[1:0]
PAIFRXMS
PAIFRX_BCLKSEL[1:0]
PAIF 1
PAIF 2
PAIFRX_RATE[2:0]
PAIFTX_RATE[2:0]
SAIF_RATE[2:0]
000000010
000000010
011000010
110001010
010001010
000001010
000100100
000001001
000000000
011111111
000000000
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
PAIFTX_BCLKSEL[1:0]
0
0
0
PAIFTXMS
SAIFMS
PAIFRXBCP
PAIFTXBCP
SAIF_BCLKSEL[1:0]
SAIF 1
0
SAIFMS_CLKSEL[1:0]
PAIFRXLRP
PAIFTXLRP
SAIFLRP
PAIFRXWL[1:0]
PAIFRXFMT[1:0]
PAIF 3
DAC_SRC[1:0]
PAIFTX_SRC[1:0]
SAIFTX_SRC[1:0]
DACOSR
PAIFTXWL[1:0]
SAIFWL[1:0]
PAIFTXFMT[1:0]
SAIFFMT[1:0]
DAC1SEL[1:0]
PAIF 4
0
SAIF_EN
0
SAIFBCP
SAIF 2
0
DAC3SEL[1:0]
DAC2SEL[1:0]
DAC CONTROL 1
DAC CONTROL 2
DAC CONTROL 3
DAC CONTROL 4
DAC CONTROL 5
RX2DAC_MODE
0
0
0
0
IZD
0
DZFM[2:0]
0
PL[3:0]
DEEMP[2:0]
0
1
0
DEEMPALL
1
PHASE[5:0]
MPDENB DACATC
DZCEN
0
DMUTE[2:0]
MUTEALL
DIGITAL ATTENUTATION
DACL 1
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
LDA1[7:0]
R20
R21
R22
R23
R24
R25
14
15
16
17
18
19
011111111
011111111
011111111
011111111
011111111
DIGITAL ATTENUTATION
DACR 1
RDA1[7:0]
LDA2[7:0]
RDA2[7:0]
LDA3[7:0]
RDA3[7:0]
DIGITAL ATTENUTATION
DACL 2
DIGITAL ATTENUTATION
DACR 2
DIGITAL ATTENUTATION
DACL 3
DIGITAL ATTENUTATION
DACR 3
011111111
011111111
MASTER DIGITAL
ATTENUTATION
UPDATE
VMIDSEL
MASTDA[7:0]
R28
R29
R30
1C
1D
1E
ADC CONTROL 1
SPDTXCHAN 0
ADCRATE[2:0]
ADCHPD ADCOSR AMUTEALL AMUTER AMUTEL 001000000
TXVAL_
SF1
TXVAL_ TXVAL_
SF0 OVWR
REAL_
0
0
0
0
0
0
0
TXSRC[1:0]
000000000
OVWCHAN
THROUGH
CHSTMODE[1:0]
DEEMPH[2:0]
CATCODE[7:0]
CHNUM1[1:0]
CLKACU[1:0]
ORGSAMP[3:0]
WL_MASK
CPY_N AUDIO_N CON/PRO
R31
R32
R33
R34
R35
1F
20
21
22
23
SPDTXCHAN 1
SPDTXCHAN 2
SPDTXCHAN 3
SPDTXCHAN 4
SPDTXCHAN 5
000000000
000000000
CHNUM2[1:0]
SRCNUM[3:0]
FREQ[3:0]
000000000
000110001
000001011
0
0
TXWL[2:0]
RXINSEL[1:0]
MAXWL
R36
R37
R38
24
25
26
SPDMODE
INTMASK
GPO1
0
0
1
1
1
000111001
000000000
000010000
SPDIFIN1MODE
MASK[8:0]
GPO2OP[3:0]
GPO1OP[3:0]
FILLMODE
PD Rev 4.3 August 2007
75
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
