WM8580
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
S/PDIF Transmitter clock source
5:4
TX_CLKSEL
01
00 = ADCMLCK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
6
CLKSEL_MAN
0
Clock selection auto-configuration override
0 = auto-configuration enabled, clock configuration follows
restrictions described in page 42 to page 47.
1 = auto-configuration disabled, clock configuration follows
relevant CLKSEL bits in R8 to R11.
R9
PAIF 1
09h
2:0
PAIFRX_RATE
[2:0]
010
Master Mode LRCLK Rate
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
4:3 PAIFRX_BCLKSEL
[1:0]
00
Master Mode BCLK Rate
00 = 64 BCLKs per LRCLK
01 = 32 BCLKs per LRCLK
10 = 16 BCLKs per LRCLK
11 = BCLK = System Clock
PAIF Receiver Master/Slave Mode Select
0 = Slave Mode
5
PAIFRXMS
0
1 = Master Mode
7:6
PAIFRXMS_
CLKSEL
00
PAIF Receiver Master Mode clock source
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
R10
PAIF 2
0Ah
2:0
PAIFTX_RATE
[2:0]
010
Master Mode LRCLK Rate
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
4:3 PAIFTX_BCLKSEL
[1:0]
00
Master Mode BCLKRate
00 = 64 BCLKs per LRCLK
01 = 32 BCLKs per LRCLK
10 = 16 BCLKs per LRCLK
11 = BCLK = System Clock
PAIF Transmitter Master/Slave Mode Select:
0 = Slave Mode
5
PAIFTXMS
0
1 = Master Mode
PD Rev 4.3 August 2007
78
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
