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WM8580AGEFTRV 参数 Datasheet PDF下载

WM8580AGEFTRV图片预览
型号: WM8580AGEFTRV
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道编解码器S / PDIF收发器 [Multichannel CODEC with S/PDIF Transceiver]
分类和应用: 解码器编解码器光电二极管
文件页数/大小: 97 页 / 1142 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8580  
Production Data  
Figure 35 and Figure 36 show typical power up scenarios in a real system. Both AVDD and DVDD  
must be established, and VMID must have reached the threshold Vporr before the device is ready  
and can be written to. Any writes to the device before Device Ready will be ignored.  
Figure 35 shows DVDD powering up before AVDD. Figure 36 shows AVDD powering up before  
DVDD. In both cases, the time from applying power to Device Ready is dominated by the charge  
time of VMID.  
A 4.7µF capacitor (minimum) is recommended for decoupling on VMID. The charge time for VMID  
will dominate the time required for the device to become ready after power is applied. The time  
required for VMID to reach the threshold is a function of the VMID resistor string and the decoupling  
capacitor. To reduce transient audio effects during power on, the stereo DACs on the WM8580 have  
their outputs clamped to VMID at power-on. This increases the capacitive loading of the VMID  
resistor string, as the DAC output AC coupling capacitors must be charged to VMID, and hence the  
required charge time. To ensure minimum device startup time, the VMIDSEL bit is set by default,  
thus reducing the impedance of the resistor string. If required, the VMID string can be restored to a  
high impedance state to save power once the device is ready.  
REGISTER ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R29  
ADC CONTROL 1  
1Dh  
8
VMIDSEL  
1
VMID Impedance Selection  
0 = High impedance, power  
saving  
1 = Low impedance, fast power-  
on  
DEVICE ID READBACK  
Reading from registers R0, R1 and R2 returns the device ID and revision number. R0 returns 80h,  
R1 returns 85h, R2 returns the device revision number. Device ID readback is not possible in  
continuous readback mode (CONTREAD=1).  
HARDWARE CONTROL MODE  
The WM8580 can be controlled in Hardware Control Mode or Software Control Mode. The method of  
control is determined by the state of the HWMODE pin. If the HWMODE pin is low, Software Control  
Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected.  
In Hardware Control Mode the user has limited control over the features of the WM8580. Most of the  
features will assume their default settings but some can be modified using external pins.  
HWMODE  
SWMODE  
0
1
0
1
Software Control Hardware Control  
2-wire control  
3-wire control  
Table 69 Hardware/Software Mode Setup  
DIGITAL ROUTING CONTROL  
See page 22 for a more detailed explanation of the Digital Routing Options within the WM8580. In  
Software Control Mode, the values of register bits DAC_SRC, PAIFTX_SRC and TXSRC configure  
the signal path routing between interfaces. In hardware mode, similar control can be achieved via  
pins DR1, DR2, DR3 and DR4 as detailed in Table 70 and Table 71.  
PIN  
DR1  
DR2  
0
1
DAC_SRC=S/PDIF receiver  
DAC_SRC=PAIF receiver  
PAIFTX_SRC=ADC output  
PAIFTX_SRC=S/PDIF  
receiver  
Table 70 DR1 / DR2 Operation  
PD Rev 4.3 August 2007  
72  
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