Production Data
WM8580
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4
PLLB 1
04h
8:0
PLLB_K[8:0]
100100001
Fractional (K) part of PLLB frequency ratio (R).
Value K is one 22-digit binary number spread over registers R4,
R5 and R6 as shown.
Note: PLLB_K must be set to specific values when the S/PDIF
receiver is used. Refer to S/PDIF Receive Mode Clocking
section for details.
R5
8:0
PLLB_K[17:9]
101111110
PLLB 2
05h
R6
3:0
7:4
PLLB_K[21:18]
PLLB_N[3:0]
1101
0111
PLLB 3
06h
Integer (N) part of PLLB frequency ratio (R).
Use values in the range 5 ≤ PLLB_N ≤ 13 as close as possible to
8
Note: PLLB_N must be set to specific values when the S/PDIF
receiver is used. Refer to S/PDIF Receive Mode Clocking
section for details.
R7
PLLB 4
07h
0
1
PRESCALE_B
0
0
PLL Pre-scale Divider Select
0 = Divide by 1 (PLL input clock = oscillator clock)
1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2)
Note: PRESCALE_A must be set to the same value as
PRESCALE_B in PLL S/PDIF receiver mode.
POSTSCALE_B
PLL Post-scale Divider Select
PLL S/PDIF Receiver Mode
POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK,
POSTSCALE_B is not used. Refer to Table 45.
PLL User Mode
Used in conjunction with the FREQMODE_x bits. Refer to Table
44.
4:3
FREQMODE_B
[1:0]
10
PLL Output Divider Select
PLL S/PDIF Receiver Mode
FREQMODE_A is automatically controlled. FREQMODE_B is not
used.
PLL User Mode
Used in conjunction with the POSTSCALE_x bits. Refer to Table
44.
6:5
8:7
1:0
3:2
MCLKOUTSRC
CLKOUTSRC
DAC_CLKSEL
ADC_CLKSEL
00
11
00
00
MCLK pin output source
00 = Input – Source MCLK pin
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
CLKOUT pin source
00 = No Output (tristate)
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
DAC clock source
R8
CLKSEL
08h
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
ADC clock source
00 = ADCMLCK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
PD Rev 4.3 August 2007
77
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
