Production Data
WM8580
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio interface are
applied to the left and right DACs:
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R16
DAC Control 2
10h
3:0
PL[3:0]
1001
PL[3:0]
0000
Left O/P
Right O/P
Mute
Mute
Left
0001
Mute
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Right
(L+R)/2
Mute
Mute
Mute
Left
Left
Left
Right
(L+R)/2
Mute
Left
Left
Right
Right
Right
Right
Left
Right
(L+R)/2
1100
1101
Mute
Left
(L+R)/2
(L+R)/2
1110
1111
Right
(L+R)/2
(L+R)/2
(L+R)/2
Table 19 DAC Attenuation Register (PL)
ZERO FLAG OUTPUT
Each DAC channel has a “zero detect circuit” which detects when 1024 consecutive zero samples
have been input. Should both channels of a DAC indicate a zero-detect (or if either DACPD or
DMUTE is set for that DAC), then the Zero Flag for that DAC is asserted. The DZFM register bits
determine which Zero Flag is visible on the MUTE and GPO pins.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Selects the source for ZFLAG
000 - All DACs Zero Flag
001 - DAC1 Zero Flag
010 - DAC2 Zero Flag
011 - DAC3 Zero Flag
100 - ZFLAG = 0
R16
DAC Control 2
10h
6:4
DZFM[2:0]
000
101 - ZFLAG = 0
110 - ZFLAG = 0
111 - ZFLAG = 0
Table 20 DZFM Register
PD Rev 4.3 August 2007
31
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