WM8580
Production Data
The MSB of the output data changes on the same falling edge of BCLK as the low to high LRCLK
transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with
the left channel data.
Figure 22 DSP Mode B Timing Diagram – PAIF/SAIF Transmitter Data
AUDIO INTERFACE CONTROL
The register bits controlling the audio interfaces are summarized below. Dynamically changing the
audio data format may cause erroneous operation, and is not recommended.
Interface timing is such that the input data and LRCLK are sampled on the rising edge of the
interface BCLK. Output data changes on the falling edge of the interface BCLK. By setting the
appropriate bit clock polarity control register bits, e.g. PAIFRXBCP, the polarity of BCLK may be
reversed, allowing input data and LRCLK to be sampled on the falling edge of BCLK. Setting the bit
clock polarity register for a transmit interface results in output data changing on the rising edge of
BCLK.
Similarly, the polarity of left/right clocks can be reversed by setting the appropriate left right polarity
bits, e.g. PAIFRXLRP.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R12
PAIF 3
0Ch
1:0
PAIFRXFMT
[1:0]
10
PAIF Receiver Audio Data Format
Select
11: DSP Format
10: I2S Format
01: Left justified
00: Right justified
3:2
PAIFRXWL
[1:0]
10
PAIF Receiver Audio Data Word
Length
11: 32 bits (see Note 1,2)
10: 24 bits
01: 20 bits
00: 16 bits
4
PAIFRXLRP
PAIFRXBCP
0
In LJ/RJ/I2S modes
0 = LRCLK not inverted
1 = LRCLK inverted
In DSP Format:
0 = DSP Mode A
1 = DSP Mode B
5
0
PAIF Receiver BCLK polarity
0 = BCLK not inverted
1 = BCLK inverted
PD Rev 4.3 August 2007
28
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
