WM8580
Production Data
Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz, 24-
Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
1kHz 100mVp-p
20Hz to 20kHz
100mVp-p
MIN
TYP
50
MAX
UNIT
dB
Power Supply Rejection Ratio
(See note 4)
PSRR
45
dB
ADC Performance
Full Scale Input Signal Level (for
ADC 0dB Input)
1.0 x
VREFP/5
6
Vrms
Input resistance
kΩ
pF
dB
Input capacitance
10
Signal to Noise Ratio (See
Terminology 1,2,4)
SNR
A-weighted,
@ fs = 48kHz
Unweighted,
@ fs = 48kHz
A-weighted,
90
100
97
97
dB
dB
@ fs = 48kHz, AVDD =
3.3V
A-weighted,
@ fs = 96kHz
Unweighted,
@ fs = 96kHz
A-weighted,
97
94
94
dB
dB
dB
@ fs = 96kHz, AVDD =
3.3V
A-weighted,
@ fs = 192kHz
Unweighted,
@ fs = 192kHz
A-weighted,
97
94
94
dB
dB
dB
@ fs = 192kHz, AVDD
= 3.3V
Total Harmonic Distortion
THD
DNR
1kHz, -1dB Full Scale
@ fs = 48kHz
-87
-86
-85
-80
dB
dB
dB
1kHz, -1dB Full Scale
@ fs = 96kHz
1kHz, -1dB Full Scale
@ fs = 192kHz
Dynamic Range
-60dB FS
1kHz Input
1KHz Signal
90
100
97
ADC Channel Separation
dB
dB
Channel Level Matching (See
Terminology 4)
0.1
Channel Phase Deviation
Offset Error
1kHz Signal
HPF On
0.0001
0
Degree
LSB
HPF Off
100
LSB
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
0.3 x DVDD
+1
V
V
Input HIGH level
0.7 x DVDD
-1
Input leakage current
Input capacitance
Output LOW
±0.2
5
µA
pF
V
VOL
VOH
I
OL=1mA
0.1 x DVDD
Output HIGH
I
OH= -1mA
0.9 x DVDD
V
PD Rev 4.3 August 2007
10
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