Production Data
WM8580
Notes for MFP1:
ADC_CLKSEL selected in REG 8, default is ADC_MCLK.
PAIFTXMS_CLKSEL selects PLLACLK if PAIF sources SPDIF Rx, otherwise PAIFTXMS_CLKSEL selects ADC_CLK
(register 8)
3. MFP2 usage can be described as follows:
IF
(ADC_CLKSEL ≠ ADCMCLK)
(controlled by reg 8)
(controlled by reg 8)
(controlled by reg 8)
AND
AND
(TX_CLKSEL ≠ ADCMCLK)
(SAIFMS_CLKSEL ≠ ADCMCLK) THEN
MFP2 = GPO2;
ELSE
MFP2 = ADCMCLK;
PIN FUNCTION
PAIFTX_BCLK
ADCMCLK
SAIF_DIN
TYPE
Digital Input/Output
Digital Input
DESCRIPTION
Primary Audio Interface Transmitter (PAIFTX) Bit Clock
Master ADC clock; 256fs, 384fs, 512fs ,786fs, 1024fs or 1152fs
Secondary Audio Interface (SAIF) Receiver data input
Secondary Audio Interface (SAIF) Transmitter data output
Secondary Audio Interface (SAIF) Bit Clock
Digital Input
SAIF_DOUT
SAIF_BCLK
SAIF_LRCLK
SPDIFIN2/3/4
GPO1 – GPO10
DR1/2/3/4
Digital Output
Digital Input/Output
Digital Input/Output
Digital Input
Secondary Audio Interface (SAIF) Left/Right Word Clock
S/PDIF Receiver Input
Digital Output
Digital Input
General Purpose Output
Internal Digital Routing Configuration in Hardware Mode
ALLPD
Digital Input
Chip Powerdown in Hardware Mode
Digital Output
Recovered channel-bit for current S/PDIF sub-frame
C
Digital Output
Indicates current S/PDIF sub-frame:
1 = Sub-frame A
SFRM_CLK
0 = Sub-frame B
Digital Output
Indicates start of S/PDIF 192-frame block. High for duration of frame 0.
192BLK
Table 2 Multi-Function Pin Description
PD Rev 4.3 August 2007
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
