WM8580
Production Data
DIGITAL AUDIO INTERFACE – SLAVE MODE
tBCH
tBCL
PAIFTX_BCLK/
PAIFRX_BCLK/
SAIF_BCLK
tBCY
PAIFTX_LRCLK/
PAIFRX_LRCLK/
SAIF_BCLK
tLRSU
tDS
tLRH
DIN1/2/3/
SAIF_DIN
tDD
tDH
DOUT/
SAIF_DOUT
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK and
ADCMCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
PAIFTX_BCLK/
tBCY
50
ns
PAIFRX_BCLK/SAIF_BCLK cycle
time
PAIFTX_BCLK/
tBCH
20
20
10
ns
ns
ns
PAIFRX_BCLK/SAIF_BCLK pulse
width high
PAIFTX_BCLK/
tBCL
PAIFRX_BCLK/SAIF_BCLK pulse
width low
PAIFTX_LRCLK/
tLRSU
PAIFRX_LRCLK/SAIF_BCLK set-up
time to PAIFTX_BCLK/
PAIFRX_BCLK/SAIF_BCLK rising
edge
PAIFTX_LRCLK/
PAIFRX_LRCLK/
tLRH
10
ns
SAIF_LRCLK hold time from
PAIFTX_BCLK/
PAIFRX_BCLK/SAIF_BCLK rising
edge
DIN1/2/3/SAIF_DIN set-up time to
PAIFRX_BCLK/
tDS
10
ns
SAIF_BCLK rising edge
DIN1/2/3/SAIF_DIN hold time from
PAIFRX_BCLK/SAIF_BCLK rising
edge
tDH
10
0
ns
ns
DOUT/SAIF_DOUT propagation
delay from
tDD
10
PAIFTX_BCLK/SAIF_BCLK falling
edge
Table 5 Digital Audio Data Timing – Slave Mode
PD Rev 4.3 August 2007
14
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
