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WM8569GEDSV 参数 Datasheet PDF下载

WM8569GEDSV图片预览
型号: WM8569GEDSV
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz立体声编解码器与音量控制 [24-bit, 192kHz Stereo CODEC with Volume Control]
分类和应用: 解码器编解码器
文件页数/大小: 36 页 / 417 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8569  
Product Preview  
DIGITAL AUDIO INTERFACE  
MASTER AND SLAVE MODES  
The audio interface operates in either Slave or Master mode, selectable using the DACMS and  
ADCMS control bits. In both Master and Slave modes DIN is always an input to the WM8569 and  
DOUT is always an output. The default is Slave mode.  
In Slave mode, DACLRC, ADCLRC, DACBCLK and ADCBCLK are inputs to the WM8569 (Figure 9).  
DIN and DACLRC are sampled by the WM8569 on the rising edge of DACBCLK. ADC data is output  
on DOUT and changes on the falling edge of ADCBCLK.  
By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN is sampled  
on the falling edge of DACBCLK. By setting the control bit ADCBCP, the polarity of ADCBCLK may  
be reversed so that DOUT changes on the rising edge of ADCBCLK.  
Figure 9 Slave Mode  
In Master mode, DACLRC, ADCLRC, DACBCLK and ADCBCLK are outputs from the WM8569  
(Figure 10). DACLRC, ADCLRC, DACBCLK and ADCBCLK are generated by the WM8569. DIN is  
sampled by the WM8569 on the rising edge of DACBCLK so the controller must output DAC data  
that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on the  
falling edge of ADCBCLK.  
By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN is sampled  
on the falling edge of DACBCLK. By setting the control bit ADCBCP, the polarity of ADCBCLK may  
be reversed so that DOUT changes on the rising edge of ADCBCLK.  
Figure 10 Master Mode  
PP Rev 1.1 December 2005  
16  
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