WM8569
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MPU INTERFACE TIMING
Figure 6 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise
stated
PARAMETER
SCLK/IWL rising edge to CSB/IDF rising edge
SCLK/IWL pulse cycle time
SYMBOL
tSCS
MIN
60
80
30
30
20
20
20
20
20
TYP
MAX
UNIT
ns
tSCY
ns
SCLK/IWL pulse width low
tSCL
ns
SCLK/IWL pulse width high
tSCH
ns
SDIN/DM to SCLK/IWL set-up time
SCLK/IWL to SDIN/DM hold time
CSB/IDF pulse width low
tDSU
ns
tDHO
tCSL
ns
ns
CSB/IDF pulse width high
tCSH
ns
CSB/IDF rising to SCLK/IWL rising
tCSS
ns
Table 4 3-Wire SPI Compatible Control Interface Input Timing Information
PP Rev 1.1 December 2005
12
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
