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WM8569
DEVICE DESCRIPTION
INTRODUCTION
WM8569 is a complete 2-channel audio codec, including digital interpolation and decimation filters,
multi-bit sigma delta stereo ADC, and switched capacitor multi-bit sigma delta DAC with volume
control and output smoothing filter.
The device is implemented as a separate stereo DAC and a stereo ADC in a single package and
controlled by a single 3-wire software or hardware interface.
The DAC has its own data input DIN, DAC word clock DACLRC, DAC bit clock DACBCLK and DAC
master clock DACMCLK while the stereo ADC has its own data output DOUT, word clock ADCLRC,
bit clock ADCBCLK and ADC master clock ADCMCLK. This allows the ADC and DAC to operate
independently.
The Audio Interface may be configured to operate in either master or slave mode. In Slave mode
DACLRC/ADCLRC and DACBCLK/ADCBCLK are all inputs. In Master mode DACLRC/ADCLRC and
DACBCLK/ADCBCLK are all outputs.
The DAC has its own digital volume control that is adjustable in 0.5dB steps. A zero cross detect
circuit is provided. The digital volume control detects a transition through the zero point before
updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values change.
Control of internal functionality of the device is by 3-wire serial or pin programmable control interface.
Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC,
for operation of both the ADC and DAC master clocks of 256fs, 384fs, 512fs and 768fs is provided.
In Slave mode, selection between clock rates is automatically controlled. In master mode, the
sample rate is set by control bits RATE. Audio sample rates (fs) from less than 8kHz up to 192kHz
are allowed for the DAC and from less than 32kHz up to 96kHz for the ADC, provided the appropriate
master clock is input.
The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP
serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the ADC and DAC
MCLK input pin(s) with no software configuration necessary. In a system where there are a number
of possible sources for the reference clock it is recommended that the clock source with the lowest
jitter be used to optimise the performance of the ADC and DAC.
The DAC master clock for WM8569 supports audio sampling rates from 128fs to 768fs, where fs is
the audio sampling frequency (DACLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
ADC master clock for WM8569 supports audio sampling rates from 256fs to 768fs, where fs is the
audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master clock is
used to operate the digital filters and the noise shaping circuits.
In Slave mode the WM8569 has a master clock detection circuit that automatically determines the
relationship between the system clock frequency and the sampling rate (to within +/- 32 master
clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The master
clocks must be synchronised with LRC, although the WM8569 is tolerant of phase variations or jitter
on this clock. Table 5 shows the typical master clock frequency inputs for the WM8569.
The signal processing for the WM8569 typically operates at an oversampling rate of 128fs for both
ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g.
for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is
recommended that the user set the ADCOSR bit. This changes the ADC signal processing
oversample rate to 64fs.
PP Rev 1.1 December 2005
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
