WM8569
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1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
DIN1/2/3/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 12 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of DIN is sampled by the WM8569 on the second rising edge of DACBCLK
following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the
first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising
edge of ADCBCLK. LRC are low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
1 BCLK
1 BCLK
DIN1/2/3/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 13 I2S Mode Timing Diagram
DSP MODE A
In DSP mode A, the MSB of DAC left channel data is sampled by the WM8569 on the second rising
edge on DACBCLK following a DACLRC rising edge. DAC right channel follows DAC left channel
(Figure 14).
Figure 14 DSP Mode A Timing Diagram – DAC Data Input
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 15)
PP Rev 1.1 December 2005
18
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
