Product Preview
WM8569
DACBCLK/
ADCBCLK
(Output)
t
DACLRC/
ADCLRC
(Output)
DL
t
DDA
DOUT
DIN
t
t
DST
DHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
DACLRC/ADCLRC
propagation delay from
DACBCLK/ADCBCLK
falling edge
tDL
0
10
ns
DOUT propagation delay
from ADCBCLK falling edge
tDDA
tDST
tDHT
0
10
ns
ns
ns
DIN setup time to
DACBCLK rising edge
10
10
DIN hold time from
DACBCLK rising edge
Table 2 Digital Audio Data Timing – Master Mode
PP Rev 1.1 December 2005
9
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
