WM8352
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC Companding enable
REFER TO
R113 (71h)
ADC DAC
COMP
7
DAC_COMP
0
0 = disabled
1 = enabled
6
DAC_COMPMODE
0
DAC Companding mode select:
0 = μ-law
1 = A-law
(Note: Setting DAC_COMPMODE=1 selects 8-bit
mode when DAC_COMP=0 and ADC_COMP=0)
5
4
ADC_COMP
0
0
ADC Companding enable
0 = disabled
1 = enabled
ADC_COMPMODE
ADC Companding mode select:
0 = μ-law
1 = A-law
(Note: Setting ADC_COMPMODE=1 selects 8-bit
mode when DAC_COMP=0 and ADC_COMP=0)
0
LOOPBACK
0
Digital Loopback Function
0 = No loopback.
1 = Loopback enabled, ADC data output is fed
directly into DAC data input.
Register 71h ADC DAC COMP
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R114 (72h)
AI ADC
Control
7
AIFADC_PD
0
Enables a pull down on ADC data pin
0 = disabled
1 = enabled
6
5
4
3
AIFADCL_SRC
AIFADCR_SRC
0
1
Selects Left channel ADC output.
0 = ADC Left channel
1 = ADC Right channel
Selects Right channel ADC output.
0 = ADC Left channel
1 = ADC Right channel
AIFADC_TDM_CHAN
AIFADC_TDM
0
0
ADCDAT TDM Channel Select
0 = ADCDAT outputs data on slot 0
1 = ADCDAT outputs data on slot 1
ADC TDM Enable
0 = Normal ADCDAT operation
1 = TDM enabled on ADCDAT
Register 72h AI ADC Control
PD, February 2011, Rev 4.4
262
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
