Production Data
WM8352
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Beep mixer enable
REFER TO
R111 (6Fh)
BEEP
Volume
15
IN3R_TO_OUT2R
0
0 = disabled
1 = enabled
7:5
IN3R_OUT2R_VOL[2:0]
000
Beep mixer volume:
000 = -15dB
… in +3dB steps
111 = +6dB
Register 6Fh BEEP Volume
REGISTER
ADDRESS
BIT
15
LABEL
AIF_BCLK_INV
AIF_TRI
DEFAULT
DESCRIPTION
REFER TO
R112 (70h)
AI Formating
0
0
0 = normal
1 = inverted
13
Sets Output enables for LRCLK and BCLK and
ADCDAT to inactive state
0 = normal
1 = forces pins to Hi-Z
LRCLK clock polarity
0 = normal
12
AIF_LRCLK_INV
0
1 = inverted
DSP Mode – mode A/B select
0 = MSB is available on 2nd BCLK rising edge after
LRCLK rising edge (mode A)
1 = MSB is available on 1st BCLK rising edge after
LRCLK rising edge (mode B)
11:10
AIF_WL[1:0]
10
Data word length
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
Note: When using the Right-Justified data format
(FMT=00), the maximum word length is 24 bits.
9:8
AIF_FMT[1:0]
10
00 = Right-justified
01 = Left justified
10 = I2S
11 = DSP / PCM mode
Register 70h AI Formating
PD, February 2011, Rev 4.4
261
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
