WM8352
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R106 (6Ah)
OUT2L
Volume
15
OUT2L_ENA
0
OUT2L enable
0 = disabled
1 = enabled
14
13
OUT2L_MUTE
OUT2L_ZC
0
0
0
OUT2L mute:
0 = normal operation
1 = mute
OUT2L volume zero cross enable
0 = Change gain immediately
1 = Change gain on zero cross only
8
OUT2_VU
OUT2L and OUT2R volumes do not update until a 1
is written to either OUT2_VU register bits.
7:2
OUT2L_VOL[5:0]
11_1001 OUT2L volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
Register 6Ah OUT2L Volume
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R107 (6Bh)
OUT2R
Volume
15
OUT2R_ENA
0
0
0
0
OUT2R enable
0 = disabled
1 = enabled
14
13
10
OUT2R_MUTE
OUT2R_ZC
OUT2R mute:
0 = normal operation
1 = mute
OUT2R volume zero cross enable
0 = Change gain immediately
1 = Change gain on zero cross only
Enable OUT2R inverting amplifier
0 = disabled
OUT2R_INV
1 = enabled
This register must be set to 0 when using the non-
inverting MIXOUT2R to OUT2R path.
This register must be set to 1 when using the
inverting MIXOUT2R to OUT2R path.
9
OUT2R_INV_MUTE
1
Mute output of PGA to inverting amplifier.
0 = PGA output goes to inverting amplifier
1 = PGA output goes to output driver
This register must be set to 0 when using the
inverting MIXOUT2R to OUT2R path.
This register must be set to 1 when using the non-
inverting MIXOUT2R to OUT2R path.
8
OUT2_VU
0
OUT2L and OUT2R volumes do not update until a
1 is written to either OUT2_VU register bits.
7:2
OUT2R_VOL[5:0]
11_1001 OUT2R volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
Register 6Bh OUT2R Volume
PD, February 2011, Rev 4.4
260
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