Production Data
WM8326
23.2.9 OTP MEMORY INTERRUPTS
The primary OTP_INT interrupt comprises two secondary interrupts as described in Section 14.5. The
secondary interrupt bits are defined in Table 73.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a OTP_INT interrupt. The secondary interrupt bits in R16402
(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16402
(4012h)
BIT
LABEL
DESCRIPTION
OTP / ICE Command End interrupt
(Rising Edge triggered)
OTP_CMD_END_EINT
5
Interrupt Status
2
Note: Cleared when a ‘1’ is written.
OTP / ICE Command Fail interrupt
(Rising Edge triggered)
OTP_ERR_EINT
4
5
Note: Cleared when a ‘1’ is written.
Interrupt mask.
R16410
(401Ah)
IM_OTP_CMD_END_EINT
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
2 Mask
Default value is 1 (masked)
Interrupt mask.
IM_OTP_ERR_EINT
4
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 73 OTP Memory Interrupts
23.2.10 HIGH CURRENT INTERRUPTS
The primary HC_INT interrupt comprises two secondary interrupts as described in Section 15.12. The
secondary interrupt bits are defined in Table 74.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a HC_INT interrupt. The secondary interrupt bits in R16404
(4014h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16404
(4014h)
BIT
LABEL
HC_DC2_EINT
DESCRIPTION
DC-DC2 High Current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
DC-DC1 High Current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
9
Interrupt Status
4
HC_DC1_EINT
8
9
R16412
(401Ch)
IM_HC_DC2_EINT
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
4 Mask
Default value is 1 (masked)
Interrupt mask.
IM_HC_DC1_EINT
8
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 74 Overcurrent Interrupts
PD, June 2012, Rev 4.0
127
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