欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM8326GEFL/V 参数 Datasheet PDF下载

WM8326GEFL/V图片预览
型号: WM8326GEFL/V
PDF下载: 下载PDF文件 查看货源
内容描述: 处理器电源管理子系统 [Processor Power Management Subsystem]
分类和应用:
文件页数/大小: 255 页 / 1340 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8326GEFL/V的Datasheet PDF文件第121页浏览型号WM8326GEFL/V的Datasheet PDF文件第122页浏览型号WM8326GEFL/V的Datasheet PDF文件第123页浏览型号WM8326GEFL/V的Datasheet PDF文件第124页浏览型号WM8326GEFL/V的Datasheet PDF文件第126页浏览型号WM8326GEFL/V的Datasheet PDF文件第127页浏览型号WM8326GEFL/V的Datasheet PDF文件第128页浏览型号WM8326GEFL/V的Datasheet PDF文件第129页  
Production Data  
WM8326  
23.2.5 WATCHDOG INTERRUPTS  
The primary WDOG_INT interrupt comprises a single secondary interrupt as described in Section 25.  
The secondary interrupt bit is defined in Table 69.  
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event  
is masked and does not trigger a WDOG_INT interrupt. The secondary interrupt bit in R16401  
(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by  
default.  
ADDRESS  
R16401  
(4011h)  
BIT  
LABEL  
DESCRIPTION  
Watchdog timeout interrupt.  
(Rising Edge triggered)  
WDOG_TO_EINT  
11  
Interrupt Status  
1
Note: Cleared when a ‘1’ is written.  
R16409  
(4019h)  
IM_WDOG_TO_EINT  
Interrupt mask.  
11  
0 = Do not mask interrupt.  
1 = Mask interrupt.  
Interrupt Status  
1 Mask  
Default value is 1 (masked)  
Table 69 Watchdog Timer Interrupts  
23.2.6 AUXADC INTERRUPTS  
The primary AUXADC_INT interrupt comprises five secondary interrupts as described in Section 18.5.  
The secondary interrupt bits are defined in Table 70.  
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt  
event is masked and does not trigger a AUXADC_INT interrupt. The secondary interrupt bits in  
R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all  
masked by default.  
ADDRESS  
R16401  
(4011h)  
BIT  
LABEL  
DESCRIPTION  
AUXADC Data Ready interrupt  
(Rising Edge triggered)  
AUXADC_DATA_EINT  
8
Interrupt Status  
1
Note: Cleared when a ‘1’ is written.  
AUXADC Digital Comparator n interrupt  
(Trigger is controlled by DCMPn_GT)  
Note: Cleared when a ‘1’ is written.  
Interrupt mask.  
AUXADC_DCOMPn_EINT  
7:4  
8
R16409  
(4019h)  
IM_AUXADC_DATA_EINT  
0 = Do not mask interrupt.  
1 = Mask interrupt.  
Interrupt Status  
1 Mask  
Default value is 1 (masked)  
Interrupt mask.  
IM_AUXADC_DCOMPn_EI  
7:4  
NT  
0 = Do not mask interrupt.  
1 = Mask interrupt.  
Default value is 1 (masked)  
Note: n is a number between 1 and 4 that identifies the individual Comparator.  
Table 70 AUXADC Interrupts  
PD, June 2012, Rev 4.0  
125  
w
 复制成功!