WM8326
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23.2.7 POWER PATH MANAGEMENT INTERRUPTS
The primary PPM_INT interrupt comprises a single secondary interrupt as described in Section 17.2.
The secondary interrupt bit is defined in Table 71.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger a PPM_INT interrupt. The secondary interrupt bit in R16401 (4011h)
are valid regardless of whether the mask bit is set. The secondary interrupt is masked by default.
ADDRESS
R16401
(4011h)
BIT
LABEL
DESCRIPTION
Power Path SYSLO interrupt
(Rising Edge triggered)
PPM_SYSLO_EINT
15
Interrupt Status
1
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
IM_PPM_SYSLO_EINT
Interrupt mask.
15
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
1 Mask
Default value is 1 (masked)
Table 71 Power Path Management Interrupts
23.2.8 REAL TIME CLOCK AND CRYSTAL OSCILLATOR INTERRUPTS
The primary RTC_INT interrupt comprises four secondary interrupts as described in Section 20.3. The
secondary interrupt bits are defined in Table 72.
Each of the secondary interrupts can be masked except for XTAL_TAMPER_EINT, which cannot be
masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a
RTC_INT interrupt. The secondary interrupt bits in R16401 (4011h) and R16404 (4014h) are valid
regardless of whether the mask bit is set.
The secondary interrupts are all masked by default, except for XTAL_TAMPER_EINT, which cannot
be masked.
ADDRESS
R16401
BIT
LABEL
DESCRIPTION
RTC Periodic interrupt
RTC_PER_EINT
3
(4011h)
(Rising Edge triggered)
Interrupt Status
1
Note: Cleared when a ‘1’ is written.
RTC Alarm interrupt
RTC_ALM_EINT
2
7
6
3
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Crystal Oscillator Start Failure interrupt
(Rising Edge triggered)
R16404
(4014h)
XTAL_START_EINT
XTAL_TAMPER_EINT
IM_RTC_PER_EINT
Interrupt Status
4
Note: Cleared when a ‘1’ is written.
Crystal Oscillator Tamper interrupt
(Rising and Falling Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
R16409
(4019h)
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
1 Mask
Default value is 1 (masked)
Interrupt mask.
IM_RTC_ALM_EINT
2
7
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
R16412
(401Ch)
IM_XTAL_START_EINT
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
4 Mask
Default value is 1 (masked)
Table 72 Real Time Clock (RTC) and Crystal Oscillator (XTAL) Interrupts
PD, June 2012, Rev 4.0
126
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