WM8326
Production Data
VPVDD
VSYSOK
VSYSLO
VSHUTDOWN
time
time
time
SYSOK (SYSLO)
SHUTDOWN
Figure 27 PVDD Monitoring
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
SYSLO Error Action
R16385
(4001h)
SYSLO_ERR_
ACT
15:14
00
Selects the action taken when SYSLO is
asserted
PVDD
Control
00 = Interrupt
01 = WAKE transition
10 = Reserved
11 = OFF transition
SYSLO Status
SYSLO_STS
11
0
0 = Normal
1 = PVDD is below SYSLO threshold
SYSLO threshold (falling PVDD)
SYSLO_THR
[2:0]
6:4
010
This is the falling PVDD voltage at which
SYSLO will be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
SYSOK_THR
[2:0]
SYSOK threshold (rising PVDD)
2:0
101
This is the rising PVDD voltage at which
SYSOK will be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
Note that the SYSOK hysteresis margin is
added to these threshold levels.
Table 78 PVDD Monitoring Control
PD, June 2012, Rev 4.0
134
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
