Production Data
WM8326
24.4 SUPPLY VOLTAGE MONITORING
The WM8326 includes a number of mechanisms to prevent the system from starting up, or to force it
to shut down, when the power sources are critically low.
The internal regulator LDO12 is powered from an internal domain equivalent to PVDD and generates
an internal supply (VPMIC) to support various “always-on” functions. In the absence of the PVDD
supply, LDO12 can be powered from a backup battery. (Note that PVDD is not maintained by the
backup battery.) The VPMIC monitoring function controls the Power-On Reset circuit, which sets the
threshold below which the WM8326 cannot operate.
The operation of the VPMIC monitoring circuit is illustrated in Figure 26. The internal signal P¯O¯¯R¯R¯S¯¯T
is governed by the VPOR thresholds. These determine when the WM8326 is kept in the NO POWER
state. The internal signal P¯¯M¯I¯C¯R¯S¯T¯ is governed by the VRES thresholds. These determine when the
WM8326 is kept in the BACKUP state.
The VPMIC monitoring thresholds illustrated in Figure 26 are fixed. The voltage levels are defined in
the Electrical Characteristics - see Section 7.3.
Figure 26 VPMIC Monitoring
The operation of the PVDD monitoring circuit is illustrated in Figure 27. The VSHUTDOWN threshold is the
voltage below which the WM8326 forces an OFF transition. This threshold voltage is fixed and is
defined in the Electrical Characteristics - see Section 7.3.
The VSYSOK threshold is the level at which the internal signal SYSOK is asserted. Any ON request will
be inhibited if SYSOK is not set. The VSYSOK threshold can be set using the SYSOK_THR register field
in accordance with the minimum voltage requirements of the application. Note that a hysteresis
margin is added to the SYSOK_THR setting; see Section 7.3 for details.
The VSYSLO threshold is the level at which the internal signal SYSLO is asserted. This indicates a
PVDD undervoltage condition, at which a selectable response can be initiated. The VSYSLO threshold
can be set using the SYSLO_THR register field. The action taken under this undervoltage condition is
selected using the SYSLO_ERR_ACT register field, as defined in Table 78. An Interrupt event is
associated with the SYSLO condition - see Section 17.2.
The SYSLO status can be read from the SYSLO_STS register bit. This bit is asserted when PVDD is
below the SYSLO threshold.
The WM8326 can also indicate the status of the SYSOK signal via a GPIO pin configured as a “PVDD
Good” output (see Section 21). A GPIO pin configured as “PVDD Good” output will be asserted when
the PVDD is above the SYSOK threshold.
PD, June 2012, Rev 4.0
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
