WM8321
Production Data
12 CONTROL INTERFACE
12.1 GENERAL DESCRIPTION
The WM8321 is controlled by writing to its control registers. Readback is available for all registers,
including Chip ID, power management status and GPIO status. The control interface can operate as a
2-wire (I2C) or 4-wire (SPI) control interface. Readback is provided on the bi-directional pin SDA1 in
2-wire (I2C) mode. The WM8321 Control Interface is powered by the DBVDD power domain.
The control interface mode is determined by the logic level on the CIFMODE pin as shown in Table 9.
CIFMODE
Low
INTERFACE FORMAT
2-wire (I2C) mode
4-wire (SPI) mode
High
Table 9 Control Interface Mode Selection
12.2 2-WIRE (I2C) CONTROL MODE
In 2-wire (I2C) mode, the WM8321 is a slave device on the control interface; SCLK1 is a clock input,
while SDA1 is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple
masters) on the same interface, the WM8321 transmits logic 1 by tri-stating the SDA1 pin, rather than
pulling it high. An external pull-up resistor is required to pull the SDA1 line high so that the logic 1 can
be recognised by the master.
In order to allow many devices to share a single 2-wire control bus, every device on the bus has a
unique 8-bit device ID (this is not the same as the 16-bit address of each register in the WM8321).
The device ID is determined by the logic level on the C¯¯S pin as shown in Table 10. The LSB of the
device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.
C¯¯S
DEVICE ID
Low
High
0110 100x = 68h(write) / 69h(read)
0110 110x = 6Ch(write) / 6Dh(read)
Table 10 Control Interface Device ID Selection
The WM8321 operates as a slave device only. The controller indicates the start of data transfer with a
high to low transition on SDA1 while SCLK1 remains high. This indicates that a device ID, register
address and data will follow. The WM8321 responds to the start condition and shifts in the next eight
bits on SDA1 (8-bit device ID including Read/Write bit, MSB first). If the device ID received matches
the device ID of the WM8321, then the WM8321 responds by pulling SDA1 low on the next clock
pulse (ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only mode,
the WM8321 returns to the idle condition and waits for a new start condition and valid address.
If the device ID matches the device ID of the WM8321, the data transfer continues as described
below. The controller indicates the end of data transfer with a low to high transition on SDA1 while
SCLK1 remains high. After receiving a complete address and data sequence the WM8321 returns to
the idle state and waits for another start condition. If a start or stop condition is detected out of
sequence at any point during data transfer (i.e. SDA1 changes while SCLK1 is high), the device
returns to the idle condition.
The WM8321 supports the following read and write operations:
Single write
Single read
Multiple write using auto-increment
Multiple read using auto-increment
PD, February 2012, Rev 4.0
40
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
