Production Data
WM8321
11.6 ON PIN FUNCTION
The O¯¯N pin is intended for connection to the master power switch on the user’s application. It can be
used to start-up the WM8321 from the SLEEP or OFF states and also to power down the system.
This pin operates on the LDO12 (VPMIC) power domain and has an internal pull-up resistor. This pin
is asserted by shorting it to GND. A de-bounce circuit is provided on this input pin.
The behaviour of the O¯¯N pin is programmable. The primary action taken on asserting this pin is
determined by the ON_PIN_PRIMACT register field. Note that the ON_PIN_INT interrupt event is
always raised when the O¯¯N pin is asserted.
If the pin is held asserted for longer than the timeout period set by ON_PIN_TO, then a secondary
action is executed. The secondary action is determined by the ON_PIN_SECACT register field.
If the pin is held asserted for a further timeout period, then a tertiary action is executed. The tertiary
action is not programmable, and is to generate an OFF request.
The status of the O¯¯N pin can be read at any time via the ON_PIN_STS register.
Note that the O¯¯N pin control registers are locked by the WM8321 User Key. These registers can only
be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R16389
(4005h) ON
Pin Control
ON_PIN_SECACT
Secondary action of O¯¯N pin (taken
after 1 timeout period)
9:8
01
00 = Interrupt
01 = ON request
10 = OFF request
11 = Reserved
Protected by user key
Primary action of O¯¯N pin
00 = Ignore
ON_PIN_PRIMACT
5:4
00
01 = ON request
10 = OFF request
11 = Reserved
Note that an Interrupt is always
raised.
Protected by user key
Current status of O¯¯N pin
0 = Asserted (logic 0)
1 = Not asserted (logic 1)
O¯¯N pin timeout period
00 = 1s
ON_PIN_STS
ON_PIN_TO
3
0
1:0
00
01 = 2s
10 = 4s
11 = 8s
Protected by user key
Table 5 ON Pin Control Registers
The O¯¯N pin interrupt event is always raised as part of the primary action when the O¯¯N pin is asserted
or de-asserted. (Note that the O¯¯N pin interrupt is raised on the rising and falling edges of this O¯¯N pin
input signal.) The O¯¯N pin interrupt is a selectable option as the secondary action.
The O¯¯N pin interrupt event is indicated by the ON_PIN_CINT register field. This secondary interrupt
triggers a primary ON Pin Interrupt, ON_PIN_INT (see Section 23). This can be masked by setting the
mask bit as described in Table 6.
PD, February 2012, Rev 4.0
37
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
