Production Data
WM8321
The WM8321 can generate an Auxiliary Reset output via a GPIO pin configured as “Auxiliary Reset”
output (see Section 21). This signal is asserted in the OFF state. The status of the Auxiliary Reset in
the SLEEP state is configurable, using the AUXRST_SLPENA register bit as defined in Table 8.
ADDRESS
R16390 (4006h)
Reset Control
BIT
LABEL
DEFAULT
DESCRIPTION
AUXRST_SLPE
NA
Sets the output status of Auxiliary
Reset (GPIO) function in SLEEP
6
1
0 = Auxiliary Reset not asserted
1 = Auxiliary Reset asserted
Protected by user key
Table 8 Auxiliary Reset (GPIO) Control
The timing details of the R¯¯E¯S¯E¯T¯ pin relative to an ON state transition are illustrated in Figure 6.
Power State
RESET pin
OFF
State Transition
ON
Time
Time delay set by
PWRSTATE_DELAY
1ms or 10ms
ON transition.
Nominal duration = 5 x 2ms
RESET delay set by RST_DUR
3ms, 11ms, 51ms or 101ms
Figure 6 RESET Pin Output
PD, February 2012, Rev 4.0
39
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
