WM8321
Production Data
The interrupt logic is illustrated in Figure 24.
IRQ mask bit
IM_IRQ
“mask” register bit
(read/write)
e.g. IM_RTC_ALM_EINT
“mask” register bit
(read/write)
e.g. IM_RTC_INT
event / fault
condition sets
secondary interrupt
e.g. RTC Alarm
AND
AND
OR
IRQ pin
OR
NOR
event-level register
bit (read only)
e.g. RTC_ALM_EINT
Primary interrupt
register bit
(read only)
e.g. RTC_INT
Writing ‘1’ to this bit
clears the
secondary interrupt
other secondary
interrupts
e.g. RTC_PER_EINT
other primary interrupts
e.g. WDOG_INT,
AUXADC_INT
Figure 24 Interrupt Logic
Following the assertion of the I¯R¯Q¯ pin to indicate an Interrupt event, the host processor can determine
which primary interrupt caused the event by reading the primary interrupt register R16400 (4010h).
This register is defined in Section 23.1.
After reading the primary interrupt register, the host processor must read the corresponding
secondary interrupt register(s) in order to determine which specific event caused the I¯R¯Q¯ pin to be
asserted. The host processor clears the secondary interrupt bit by writing a logic 1 to that bit.
23.1 PRIMARY INTERRUPTS
The primary interrupts are defined in Table 64. These bits are Read Only. They are set when any of
the associated unmasked secondary interrupts is set. They can only be reset when all of the
associated secondary resets are cleared or masked.
Each primary interrupt can be masked. When a mask bit is set, the corresponding primary interrupt is
masked and does not cause the I¯R¯Q¯ pin to be asserted. The primary interrupt bits in R16408 (4018h)
are valid regardless of whether the mask bit is set. The primary interrupts are all masked by default.
ADDRESS
R16400
(4010h)
BIT
LABEL
DESCRIPTION
Power State primary interrupt
0 = No interrupt
PS_INT
15
System
Interrupts
1 = Interrupt is asserted
Thermal primary interrupt
0 = No interrupt
TEMP_INT
GP_INT
14
13
12
11
8
1 = Interrupt is asserted
GPIO primary interrupt
0 = No interrupt
1 = Interrupt is asserted
ON Pin primary interrupt
0 = No interrupt
ON_PIN_INT
WDOG_INT
AUXADC_INT
1 = Interrupt is asserted
Watchdog primary interrupt
0 = No interrupt
1 = Interrupt is asserted
AUXADC primary interrupt
0 = No interrupt
1 = Interrupt is asserted
PD, February 2012, Rev 4.0
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
