WM8321
Production Data
23.2.5 WATCHDOG INTERRUPTS
The primary WDOG_INT interrupt comprises a single secondary interrupt as described in Section 25.
The secondary interrupt bit is defined in Table 69.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger a WDOG_INT interrupt. The secondary interrupt bit in R16401
(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by
default.
ADDRESS
R16401
(4011h)
BIT
LABEL
DESCRIPTION
Watchdog timeout interrupt.
(Rising Edge triggered)
WDOG_TO_EINT
11
Interrupt Status
1
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
IM_WDOG_TO_EINT
Interrupt mask.
11
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
1 Mask
Default value is 1 (masked)
Table 69 Watchdog Timer Interrupts
23.2.6 AUXADC INTERRUPTS
The primary AUXADC_INT interrupt comprises five secondary interrupts as described in Section 18.5.
The secondary interrupt bits are defined in Table 70.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a AUXADC_INT interrupt. The secondary interrupt bits in
R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all
masked by default.
ADDRESS
R16401
(4011h)
BIT
LABEL
DESCRIPTION
AUXADC Data Ready interrupt
(Rising Edge triggered)
AUXADC_DATA_EINT
8
Interrupt Status
1
Note: Cleared when a ‘1’ is written.
AUXADC Digital Comparator n interrupt
(Trigger is controlled by DCMPn_GT)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
AUXADC_DCOMPn_EINT
7:4
8
R16409
(4019h)
IM_AUXADC_DATA_EINT
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
1 Mask
Default value is 1 (masked)
Interrupt mask.
IM_AUXADC_DCOMPn_EI
7:4
NT
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Note: n is a number between 1 and 4 that identifies the individual Comparator.
Table 70 AUXADC Interrupts
23.2.7 POWER PATH MANAGEMENT INTERRUPTS
The primary PPM_INT interrupt comprises a single secondary interrupt as described in Section 17.2.
The secondary interrupt bit is defined in Table 71.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger a PPM_INT interrupt. The secondary interrupt bit in R16401 (4011h)
are valid regardless of whether the mask bit is set. The secondary interrupt is masked by default.
PD, February 2012, Rev 4.0
124
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