WM8216
Production Data
CDS/NON-CDS PROCESSING
For CCD type input signals, containing a fixed reference/reset level, the signal may be processed
using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise.
With CDS processing the input waveform is sampled at two different points in time for each pixel,
once during the reference/reset level and once during the video level. To sample using CDS, register
bit CDS must be set to 1 (default). This causes the signal reference to come from the video reference
level as shown in Figure 10.
The video sample is always taken on the falling edge of the input VSMP signal (VS). In CDS-mode
the reset level is sampled on the falling edge of the RSMP input signal (RS).
For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS
processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on
pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled at the same time as VSMP samples the
video level in this mode.
It should be noted that if a coupling capacitor is used on OINP or EINP in non-CDS mode, a drift in
output code will be seen, unless the input is clamped each pixel – see Reset Level Clamping section.
The drift effect can be reduced by increasing the size of coupling capacitor used or reducing the
number of samples between clamping.
Figure 10 CDS/non-CDS Input Configuration
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by a 9-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[8:0].
The gain characteristic of the WM8216 PGA is shown in Figure 11.. Figure 12 shows the maximum
device input voltage that can be gained up to match the ADC full-scale input range (default=2V).
PD Rev 4.0 March 2007
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