WM8195
Production Data
PARALLEL INTERFACE
tSTB
STB
tASU
Hi-Z
tAH
tDH
tSTAO
tSTDO
tDSU
Hi-Z
ADC DATA OUT
ADDRESS IN
DATA IN
ADC DATA OUT
REG. DATA OUT
ADC DATA OUT
OP[13:6]
tADLS
tADLH
tADHS
tADHH
DNA
tOPZ
tOPD
RNW
Figure 6 Parallel Interface Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RNW low to OP[13:6] Hi-Z
tOPZ
10
ns
Address set-up time to STB low
DNA low set-up time to STB low
Strobe low time
tASU
tADLS
tSTB
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
5
Address hold time from STB high
DNA low hold time from STB high
Data set-up time to STB low
DNA high set-up time to STB low
Data hold time from STB high
Data high hold time from STB high
RNW high to OP[13:6] output
tAH
tADLH
tDSU
tADHS
tDH
5
0
5
5
tADHH
tOPD
tSTDO
5
30
30
Data output propogation delay from
STB low
ADC data out propogation delay
from STB high
tSTAO
30
ns
Note: Parameters are measured at 50% of the rising/falling edge.
PD Rev 4.1 July 2005
12
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
