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WM2633 参数 Datasheet PDF下载

WM2633图片预览
型号: WM2633
PDF下载: 下载PDF文件 查看货源
内容描述: 字节宽并行输入, 12位电压输出DAC ,内置基准 [Byte-wide Parallel Input, 12-bit Voltage Output DAC with Internal Reference]
分类和应用:
文件页数/大小: 12 页 / 392 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM2633  
Production Data  
DEVICE DESCRIPTION  
GENERAL FUNCTION  
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to  
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference  
input voltage and the input code according to the following relationship:  
CODE  
Output voltage = 2  
(
VREF  
)
4096  
INPUT  
OUTPUT  
1111  
1111  
1111  
4095  
4096  
2
(
VREF  
)
)
:
:
1000  
1000  
0111  
0000  
0001  
0000  
1111  
2049  
4096  
(
2 VREF  
0000  
1111  
2048  
4096  
2
(
VREF  
)
= VREF  
2047  
2
2
(
(
VREF  
)
)
4096  
:
:
0000  
0000  
0000  
0001  
0000  
1
VREF  
4096  
0000  
0V  
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2  
POWER ON RESET  
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.  
BUFFER AMPLIFIER  
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a  
2kload with a 100pF load capacitance.  
EXTERNAL REFERENCE  
If an external reference is selected, the reference voltage input is buffered which makes the DAC  
input resistance independent of code. The REF pin has an input resistance of 10Mand an input  
capacitance of typically 55pF. The reference voltage determines the DAC full-scale output.  
HARDWARE CONFIGURATION OPTIONS  
The device has three configuration options that are controlled by device pins.  
DEVICE POWER DOWN  
The device can be powered-down by pulling pin NPD (pin 15) high. This powers down the DAC. This  
will reduce power consumption significantly. The NPD pin low overrides the software control bit  
PWR. When the power down function is released the device reverts to the DAC code set prior to  
power down.  
SETTLING TIME  
The settling time of the device can be controlled by pin SPD (pin 9). A ONE on pin SPD will ensure a  
FAST settling time; a ZERO will ensure a SLOW settling time. The SPD pin high overrides the  
software control bit SPD.  
SIMULTANEOUS DAC UPDATE  
The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latch. By  
writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC  
latch.  
WOLFSON MICROELECTRONICS LTD  
PD Rev 1.0 July 1999  
8