WM2633
Production Data
8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V
supply current will increase.
9. Typical supply current in powerdown mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates.
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with
a sampling frequency fS .
PARALLEL INTERFACE
tSUD
tHD
X
Data
X
X
D[0-7]
A[0-1]
NCS
tSUA
tHA
X
Address
tSUCSWE
tWWE
NWE
tSUWELD
tWLD
NLDAC
Figure 1 Timing Diagram
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
tSUCSWE
tSUD
Setup time NCS low before positive NWE edge
Data ready before positive NWE edge
Data hold after positive NWE edge
Setup time for address bits A0, A1
Positive NWE edge before NLDAC low
High pulse width of NWE
15
10
5
ns
ns
ns
ns
ns
ns
ns
tHD
tSUA
20
5
tSUWELD
tWWE
tWLD
20
23
Low pulse width of NLDAC
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
