WM2627
Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 8-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input
voltage and the input code according to the following relationship:
CODE
V
= 2
(
VREFIN
)
out
256
INPUT
OUTPUT
255
256
1111
1111
2
2
(
VREF
)
:
:
129
256
1000
1000
0111
0001
0000
1111
(VREF
)
128
256
2
(
VREF
)
= VREF
127
256
2
2
(VREF
)
)
:
:
1
0000
0000
0001
0000
(VREF
256
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ
load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code.
REFINAB and REFINCD pins have an input resistance of 10MΩ and an input capacitance of typically
5pF. The reference voltage determines the DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
DEVICE POWER DOWN
The device can be powered-down by pulling pin NPD (Pin 2) high. This powers down all DACs
overriding their individual power down settings. This will reduce power consumption to typically 10nA.
When the power down function is released the device reverts to the DAC code set prior to power
down.
SIMULTANEOUS DAC UPDATE
The NLDAC pin (Pin 3) can be held high to prevent serial word writes from updating the DAC latches.
By writing new values to multiple DACs then pulling NLDAC low, all new DAC codes are loaded into
the DAC latches simultaneously.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
