WM2627
Production Data
SERIAL INTERFACE
tWL
tWH
3
tSUC16CS
1
2
4
5
15
16
SCLK
tSUD
tHD
D15
tSUCSFS
D14
D13
D12
D1
D0
DIN
NCS
FS
tWHFS
tSUFSCLK
tSUC16FS
Figure 1 Timing Diagram
Test Conditions:
RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise)
SYMBOL
tSUCSFS
TEST CONDITIONS
MIN
10
8
TYP
MAX
UNIT
ns
Setup time NCS low before negative FS edge.
Setup time FS low before first negative SCLK edge.
tSUFSCLK
ns
Setup time, sixteenth negative SCLK edge after FS
low on which D0 is sampled before rising edge of FS.
tSUC16FS
10
10
ns
ns
Setup time, sixteenth positive SCLK edge (first
positive after D0 sampled) before NCS rising edge.
If FS is used instead of the sixteenth positive edge to
update the DAC, then the setup time is between the
FS rising edge and the NCS rising edge.
tSUC16CS
tWHCLK
tWLCLK
tSUDCLK
tHDCLK
tWHFS
Pulse duration, SCLK high.
25
25
8
ns
ns
ns
ns
ns
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
Pulse duration, FS high.
5
20
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
