Production Data
WM2625
Since a data word contains 16 bits, the sample rate for one channel is limited to
1
fs max
=
= 1.25MHz
16×
(
tWH min + tWLmin
)
For full two-channel operation, where two data words need to be transmitted per sample, this figure
is halved to 625kHz. However, the DAC settling time to 8-bit accuracy limits the response time of
the analogue output for large input step transitions.
SOFTWARE CONFIGURATION OPTIONS
Table 2 shows the composition of a 16-bit data word. D11-D4 contains the 8-bit data word, and
D14-D13 hold the programmable options. Bits D15 and D12 are used for addressing the different
latches. D3 to D0 are unused and should be set to ZERO.
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5
D4
D3
0
D2 D1 D0
R1 SPD PWR R0
New DAC value (8 bits)
0
0
0
Table 2 Register Map
PROGRAMMABLE CONVERTER SPEED
SPD (Bit 14) allows for software control of the converter speed. A ONE selects the fast mode,
where typical settling time to within ±0.5LSB of the final value is 1µs. a ZERO puts the device into
the slow mode, where typical settling time is 3µs.
PROGRAMMABLE POWER DOWN
The power down function is controlled by PWR (Bit 13). A ZERO configures the device as active,
or fully powered up, a ONE sets the device into power down mode. When the power down function
is released the device reverts to the DAC code set prior to power down.
ADDRESSING THE BUFFER AND DAC LATCHES
Data received on the serial interface is routed according to the values of bits R1 and R0, as shown
in Table 3
R1
R0
REGISTER
(BIT D15)
(BIT D12)
0
0
1
1
0
1
0
1
Write data to DAC B and buffer
Write data to buffer
Write data to DAC A and update DAC B with buffer content
Reserved
Table 3 Latch Addressing
To update both DACs simultaneously, the data intended for DAC B should first be stored in the
buffer. Subsequently, writing data to DAC A will automatically update the DAC B latch from the
buffer, so that the analogue output of both DACs will change at the same time.
When updating the two channels independently, all data written to the DAC B latch (R1 and R0 set
to ZERO) is also copied to the buffer. Thus the automatic update of DAC B when writing to DAC A
latch (R1=1, R0=0) does not change the DAC B data. Data should not be written only to the buffer
when operating in this mode.
EXAMPLES OF OPERATION
Simultaneous operation, slow mode:
1. Write data for DAC B to buffer
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5
D4
D3
0
D2 D1 D0
0
0
0
1
New DAC B value
0
0
0
2. Write new DAC A value and update DAC B from buffer simultaneously
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5
D4
D3
0
D2 D1 D0
1
0
0
0
New DAC A value
0
0
0
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
7
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
