WM2625
Production Data
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as
the digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is
expressed as a percentage of the full scale output voltage with a 10kΩ load.
8. IDD is measured while continuously writing code 128 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will
increase.
9. Slew rate results are for the lower value of the rising and falling edge slew rates
10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
11. SNR, SNRD, THD and SPFDR are measured on a synthesised sine wave at frequency fOUT generated with a sampling
frequency fs.
SERIAL INTERFACE
tWL
tWH
3
tSUC16CS
1
2
4
5
15
16
SCLK
DIN
tSUD
tHD
D15
tSUCSCK
D14
D13
D12
D1
D0
NCS
Figure 1 Timing Diagram
Test Conditions:
RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating
free-air temperature range (unless noted otherwise).
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Setup time, NCS low before first falling SCLK edge
tSUCSCK
10
ns
Setup time, 16th falling SCLK edge (when data bit D0
is sampled) before NCS rising edge.
tSUC16CS
10
ns
Pulse duration, SCLK high.
tWH
tWL
tSUD
tHD
25
25
10
10
ns
ns
ns
ns
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
4
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
