Production Data
WM2618
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode.
The data (bits D0 to D11) are written to both the double buffer and latch B.
The latch A contents and the DAC A output are not changed by this write.
3. double buffered change of both DAC outputs
Assuming that DACs A and B start at zero code (e.g., after power up), if DAC A is to be
driven to mid-scale and DAC B to full-scale, and if the outputs are to begin rising at the same
time, this can be achieved as follows:
First,
0d01 1111 1111 1111
is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale
code into the double buffer but does not change the latch B contents and the DAC B output
voltage. The latch A contents and the DAC A output are also unaffected by this write
operation.
Changing from fast to slow to fast mode changes the supply current which can glitch the
outputs, and so D14 (designated by d in the above data word) should be set to maintain the
speed mode set by the previous write.
Next,
1d0X 1000 0000 0000
is written (bit D15 on the left, D0 on the right) to the serial interface. The X in bit D12 can be
zero or one (don’t care). This writes the mid-scale code (100000000000) to latch A and also
copies the full-scale code from the double buffer to latch B. Both DAC outputs thus begin to
rise after the second write.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
