WM2618
Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital
data to analogue voltage levels (see Block Diagram). The output voltage is determined by the
reference input voltage and the input code according to the following relationship:
CODE
Output voltage = 2
(V
REF
)
4096
INPUT
OUTPUT
4095
1111
1111
1111
2(V
REF
)
4096
:
:
2049
4096
1000
1000
0111
0000
0001
0000
1111
2
(
V
REF
)
2048
4096
0000
1111
2(
V
REF
)
= VREF
2047
2(
V
REF
)
4096
:
:
1
0000
0000
0000
0001
0000
2(V
REF
)
4096
0000
0V
Table 1 Binary Code Table (0V to 2VREFIN Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably
drive a 2kΩ load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent
of code. The REFIN input resistance is 10MΩ and the REFIN input capacitance is typically
5pF. The reference voltage determines the DAC full-scale output.
SERIAL INTERFACE
When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input
data clocked in most significant bit first. The falling edge of the SCLK input shifts the data
into the input register. After 16 bits have been transferred, the next rising edge on SCLK or
NCS then transfers the data to the DAC latch. When NCS is high, input data cannot be
clocked into the input register (see Table 2).
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1
fSCLKmax =
= 20MHz
t
WCH min+ tWCL min
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the
DAC settling time to 12 bits limits the update rate for large input step transitions.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
