WM2618
Production Data
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale
(excluding the effects of zero code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any
adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or
remains constant) as a change in digital input code.
3.
4.
5.
Zero code error is the voltage output when the DAC input code is zero.
Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this
signal imposed on the zero code error and the gain error.
6.
7.
Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It
is expressed as a percentage of the full scale output voltage with a 10kΩ load.
8.
IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply
current will increase.
9.
Slew rate results are for the lower value of the rising and falling edge slew rates.
10.
Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising
and falling edges. Limits are ensured by design and characterisation, but are not production tested.
SERIAL INTERFACE
tSUCSS
NCS
tSUCS1
tSUCS2
tWCL
tWCH
SCLK
tSUDCLK
D14
tHDCLK
D13
D15
D12
D11
D0
DIN
Figure 1 Timing Diagram
Test Conditions:
RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended
operating free-air temperature range (unless noted otherwise)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Setup time NCS low before SCLK low
tSUCSS
5
ns
Setup time, falling edge of SCLK to rising edge of
NCS, external end of write
tSUSCS1
tSUSCS2
10
5
ns
ns
Setup time, rising edge of SCLK to falling edge of
NCS, start of next write cycle
Pulse duration, SCLK high
tWCL
tWCH
tSUDCLK
tHDCLK
25
25
5
ns
ns
ns
ns
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
5
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
4
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
