W9412G6JH
7.10.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6
0
A5
0
A4
0
CAS LATENCY
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
4
1
0
0
1
0
1
Reserved
2.5
1
1
0
1
1
1
Reserved
7.10.4 DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.
7.10.5 Mode Register/Extended Mode register change bits (BA0, BA1)
These bits are used to select MRS/EMRS.
BA1
0
BA0
A11-A0
0
1
x
Regular MRS Cycle
Extended MRS Cycle
Reserved
0
1
7.10.6 Extended Mode Register field
1) DLL Switch field (A0)
This bit is used to select DLL enable or disable
A0
0
DLL
Enable
Disable
1
2) Output Driver Strength Control field (A6, A1)
The 100%, 60% and 30% or matched impedance driver strength are required Extended Mode
Register Set (EMRS) as the following:
A6
0
A1
0
BUFFER STRENGTH
100% Strength
60% Strength
Reserved
0
1
1
0
1
1
30% Strength
7.10.7 Reserved field
Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to “0” for normal operation.
Reserved bits (A9, A10, A11)
These bits are reserved for future operations. They must be set to “0” for normal operation.
Publication Release Date: Nov. 29, 2011
- 16 -
Revision A03
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