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W9412G6JH-5 参数 Datasheet PDF下载

W9412G6JH-5图片预览
型号: W9412G6JH-5
PDF下载: 下载PDF文件 查看货源
内容描述: 双倍数据速率的架构;每个时钟周期2的数据传输 [Double Data Rate architecture; two data transfers per clock cycle]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率数据传输时钟
文件页数/大小: 53 页 / 1006 K
品牌: WINBOND [ WINBOND ]
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W9412G6JH  
7.10.2 Addressing Mode Select (A3)  
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the  
A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both  
addressing Mode support burst length 2, 4 and 8 words.  
A3  
0
ADDRESSING MODE  
Sequential  
1
Interleave  
7.10.2.1. Addressing Sequence of Sequential Mode  
A column access is performed by incrementing the column address input to the device. The  
address is varied by the Burst Length as the following.  
Addressing Sequence of Sequential Mode  
DATA  
Data 0  
Data 1  
Data 2  
Data 3  
Data 4  
Data 5  
Data 6  
Data 7  
ACCESS ADDRESS  
BURST LENGTH  
n
2 words (address bits is A0)  
not carried from A0 to A1  
4 words (address bit A0, A1)  
Not carried from A1 to A2  
n + 1  
n + 2  
n + 3  
n + 4  
n + 5  
n + 6  
n + 7  
8 words (address bits A2, A1 and A0)  
Not carried from A2 to A3  
7.10.2.2. Addressing Sequence for Interleave Mode  
A Column access is started from the inputted column address and is performed by interleaving the  
address bits in the sequence shown as the following.  
Addressing Sequence of Interleave Mode  
DATA  
Data 0  
Data 1  
ACCESS ADDRESS  
BURST LENGTH  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
2 words  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
Data 2  
Data 3  
Data 4  
Data 5  
Data 6  
Data 7  
4 words  
8 words  
A8 A7 A6 A5 A4 A3 A2  
A0  
A1  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3  
A8 A7 A6 A5 A4 A3  
A8 A7 A6 A5 A4 A3  
A8 A7 A6 A5 A4 A3  
A1 A0  
A2  
A2  
A1  
A0  
A0  
A2 A1  
A2 A1 A0  
Publication Release Date: Nov. 29, 2011  
Revision A03  
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