W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
MCLK output delay adjustment
MCLK_O_D [3:0]
Gate
Dela
y
MCLK_O_D [3:0]
Gate
Dela
y
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
P-0
P-1
P-2
P-3
P-4
P-5
P-6
P-7
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
N-0
N-1
N-2
N-3
N-4
N-5
N-6
N-7
[3:0]
MCLK_O_D
NOTE: “P-x” means MCLKO shift “X” gates delay by refer HCLK
positive edge, “N-x” means MCLKO shift “X” gates delay by refer HCLK
negative edge. MCLK is the output pin of MCLKO, which is an internal
signal on chip.
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