W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
Address set-up before nECS for external I/O bank 0~3
tACS [7:5] MCLK
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
2
3
4
5
6
7
[7:5]
tACS
Chip selection set-up time of external I/O bank 0~3
When ROM/Flash memory bank is configured, the access to its bank
stretches chip selection time before the nOE or new signal is activated.
tCOS [4:2]
MCLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
[4:2]
tCOS
Programmable data bus width for external I/O bank 0~3
DBWD [1:0]
Width of Data Bus
Disable bus
8-bit
[1:0]
DBWD
0
0
1
1
0
1
0
1
16-bit
RESERVED
- 74 -
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