W90N745CD/W90N745CDG
6.4
Cache Controller
The W90N745 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The I-
Cache and D-Cache have similar organization except the cache size. To raise the cache-hit ratio, these
two caches are configured two-way set associative addressing. Each cache has four words cache line
size. When a miss occurs, four words must be fetched consecutively from external memory. The
replacement algorithm is a LRU (Least Recently Used).
If disabling the I-Cache / D-Cache, these cache memories can be treated as On-Chip RAM. The
W90N745 also provides a write buffer to improve system performance. The write buffer can buffer up to
eight words of data.
6.4.1 On-Chip RAM
If I-Cache or D-Cache is disabled, it can be served as On-Chip RAM. If D-Cache is disabled, there has
4KB On-Chip RAM, its start address is 0xFFE01000. If I-Cache is disabled, there has 4KB On-Chip RAM
and the start address of this RAM is 0xFFE00000. If both the I-Cache and D-Cache are disabled, it has
8KB On-Chip RAM starting from 0xFFE00000.
The size of On-Chip RAM is depended on the I-Cache and D-Cache enable bits ICAEN, DCAEN in
Cache Control Register (CAHCON).
Table 6.4.1 The size and start address of On-Chip RAM
ON-CHIP RAM
ICAEN
DCAEN
SIZE
START ADDRESS
0
0
1
1
0
1
0
1
8KB
0xFFE0_0000
4KB
4KB
0xFFE0_0000
0xFFE0.1000
Unavailable
6.4.2 Non-Cacheable Area
Although the cache affects the entire 2GB system memory, it is sometimes necessary to define non-
cacheable areas when the consistency of data stored in memory and the cache must be ensured. To
support this, the W90N745 provides a non-cacheable area control bit in the address field, A[31].
If A[31] in the ROM/FLASH, SDRAM, or external I/O bank’s access address is “0”, then the accessed
data is cacheable. If the A [31] value is “1”, the accessed data is non-cacheable.
Publication Release Date: September 22, 2006
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Revision A2
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