W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Enable SQE Checking controls the enable of SQE checking.
The SQE checking is only available while EMC is operating on 10M
bps and half duplex mode. In other words, the EnSQE cannot affect
EMC operation, if the EMC is operating on 100M bps or full duplex
mode.
[17]
EnSQE
1’b0: Disable SQE checking while EMC is operating on 10Mbps and
half duplex mode.
1’b1: Enable SQE checking while EMC is operating on 10Mbps and
half duplex mode.
The Send PAUSE Frame controls the PAUSE control frame
transmission.
If S/W wants to send a PAUSE control frame out, the CAM entry 13,
14 and 15 must be configured first and the corresponding CAM
enable bit of CAMEN register also must be set. Then, set SDPZ to 1
enables the PAUSE control frame transmission.
The SDPZ is a self-clear bit. This means after the PAUSE control
frame transmission has completed, the SDPZ will be cleared
automatically.
[16]
SDPZ
It is recommended that only enables SPDZ while EMC is operating
on full duplex mode.
1’b0: The PAUSE control frame transmission has completed.
1’b1: Enable EMC to transmit a PAUSE control frame out.
[15:10]
[9]
Reserved
NDEF
-
The No Defer controls the enable of deferral exceed counter. If
NDEF is set to high, the deferral exceed counter is disabled. The
NDEF is only useful while EMC is operating on half duplex mode.
1’b0: The deferral exceed counter is enabled.
1’b1: The deferral exceed counter is disabled.
- 118 -
WINBOND [ WINBOND ]
